1. Field of the Invention
The present invention relates to electronic circuits and, more specifically, to a system for scanning test data into and out of electronic circuits.
2. Description of the Related Art
As the demands placed on integrated circuit devices an circuit boards on which they reside continue to increase, the need to measure the specific performance features of such devices has become particularly important in the design cycle. JTAG (Joint Test Action Group) is an industry standard for a method to test electronic circuit boards and integrated circuits. JTAG provides a single point of access to a circuit, allowing test data to be written to and to be read from predetermined test locations in the circuit.
While JTAG is commonly used in finding circuit faults during manufacturing, it is also used by developers and service personnel in debugging computer circuits. On most systems, JTAG-based debugging is available from the very first instruction after a CPU reset. As such, JTAG can even support software development.
In many ICs today, all the pins that connect to electronic logic are linked together in a set called the Boundary Scan chain. Boundary scan description language (BSDL) is used to generate commands for testing under JTAG. Boundary-scan technology is commonly used with JTAG. By using JTAG to manipulate the scan chain's external interface (inputs and outputs to other chips) it is possible to test for faults. By using JTAG to manipulate its internal interface to on-chip registers, the logic circuits in a chip can be tested. When combined with built-in self-test (BIST), the JTAG scan chain enables a low overhead, embedded solution to testing an IC for certain static faults (shorts, opens, and logic errors).
Internal JTAG (IJTAG) is a new standard that allows simpler access to a circuit than the access allowed by JTAG. Specifically, IJTAG allows access to a plurality of circuit elements (referred to as “instruments”) within a circuit by connecting the instruments through a daisy chain configuration beginning with a test access port (TAP). Under such a configuration, each instrument includes a test data in (“TDI”) and a test data out (“TDO”). Each TDI receives data from a TDO of another instrument (except for the TDI and TDO connected to the TAP).
Test data is scanned into an initial TDI from the TAP and then is scanned from instrument to instrument until it arrives at the desired instrument. Disadvantageously, however, this scanning can be time consuming for remote instruments.
Therefore, there is a need for a system for better controlling the scanning of test data into instruments in a circuit.